1. Field of the Invention
The present invention generally relates to a method for forming a contact of a semiconductor device, and more specifically, to a method for forming a contact of a semiconductor device wherein an interlayer dielectric (hereinafter, referred to as “ILD”) layer is polished using a CMP slurry having high selectivity to an oxide film in a STI (shallow trench isolation) etching process for forming a line-type storage node contact (hereinafter, referred to as “SNC”), and an ILD layer having a predetermined thickness is re-formed on the semiconductor substrate to secure a sufficient etching margin to a subsequent etching process, thereby preventing loss of a hard mask nitride film of a bit line and reducing fail of a self-aligned contact (hereinafter, referred to as “SAC”) between a storage node and a bit line.
2. Description of the Prior Art
The development of fine pattern formation technology has affected the high-integration trend of semiconductor devices, and the size of a unit cell of a semiconductor memory device has been reduced depending on high integration and high capacity of the semiconductor memory device.
Specifically, in case of DRAM (Dynamic Random Access Memory) which leads increase of integration degree, vertical structures become complicated according to reduction of memory cell size. As a result, in order to increase the effective area of a capacitor, a capacitor is formed after a bit line is formed.
In addition, when the bit line is formed, it is important to form a SNC for performing an electrical operation between a transistor and a capacitor.
The SNC is formed by a line-type SAC process. In the line-type SAC process, a bit line is patterned, an ILD layer is formed, and the semiconductor substrate is etched except a part of the ILD layer for separating a contact.
Here, in order to secure an etching margin for the etching process, the ILD layer having a predetermined thickness is required to remain on the bit line in the planarization process on the ILD layer. However, as a semiconductor device becomes microscopic, it is difficult to perform the planarization process on the ILD layer on the bit line, thereby forming the ILD layer of non-uniformity.
FIGS. 1a to 1f are diagrams illustrating a conventional method for forming a contact of a semiconductor device.
Referring to FIG. 1a, a first ILD layer 5 using an oxide film is formed on a semiconductor substrate 1 having a cell transistor (not shown) and a lower poly silicone plug 3.
As shown in FIG. 1b, the stacked structure of a barrier layer (not shown) material for bit line, a conductive layer (not shown) for bit line and a hard mask nitride film (not shown) are formed on the first ILD layer 5 of FIG. 1a, and a selectively etching is performed the stacked structure to form a bit line 13 comprising a barrier layer pattern 7 for bit line, a conductive layer pattern 9 for bit line and a hard mask nitride film pattern 11.
As shown in FIG. 1c, a bit line spacer 15 is formed at a sidewall of the bit line 13 of FIG. 1b. 
As shown in FIG. 1d, a second ILD layer 17 is formed on the semiconductor substrate including bit line of FIG. 1c. 
The second ILD layer 17 of FIG. 1d is polished using common CMP slurry. Due to the polishing process, an ILD layer having a predetermined thickness remains on the bit line 13.
The common CMP slurry including a colloidal or fumed SiO2 abrasive and additive such as KOH/NH4OH has a pH ranging from 10 to 11 and a polishing selectivity in the range of 1:4 for a nitride film: oxide film.
As shown in FIG. 1f, a SNC etching process is performed on the planarized second ILD layer 17 shown in FIG. 1e until the poly silicone plug 3 is exposed to form a SNC opening 19.
When the ILD layer is polished using the common slurry so that the ILD layer having a predetermined thickness remains on the bit line, the ILD layer on the bit line has large difference in the thickness, thereby causing loss of the hard mask nitride film in a subsequent SNC etching process.
For example, if an etching process is performed after an etching target for forming a SNC opening is determined in the ILD layer having a thick thickness formed on the bit line, the hard mask nitride 11 is severely lost on the ILD layer 17 having a thick thickness as shown in FIG. 2a. In this way, since the thickness of the hard mask nitride film becomes thinner by a SNC CMP process, errors of the bit line and SAC are generated in the etching process for forming a subsequent SN.
On the other hand, if an etching process is performed after an etching target is determined in the ILD layer having a thin thickness formed on the bit line, the upper portion of the ILD layer 17 having a thin thickness is not polished but remains on the bit line as shown in FIG. 2b. As a result, the SNC is not open.
This shortcoming generates between area difference of the SNC region and size difference of the bottom region in the etching process. As a result, it is difficult to embody uniform device characteristics on the whole surface of the wafer.